How to use iff for multiple event control

SystemVerilog
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1

The LRM references the idea of a conditional event control as follows:

always @ (posedge clk iff rst == 0 or posedge rst)

but how do I structure the code if I want both of the events to have the conditional control?

i.e.

always @ ((posedge clk or posedge rst) iff rst == 0)
2

In reply to a_stod:

You can write

always @ (posedge c1 iff r1 == 0 or posedge c2 iff r2 == 0) ...

Note that
@(posedge rat iff rst==0) is an event that can never happen.