How to Stop Overriding Constraints

SystemVerilog
1

Hi,

Is there a way that I can make sure the constraints written in the base class can not be overriden by the child class in any case.



class base_cfg_data extends uvm_object;

  `uvm_object_utils(base_cfg_data)
 
 rand int var_a;
 rand int var_b;
 rand bit ctrl_knob_1;
 rand bit ctrl_knob_2;

 constraint c_var_a {
  if(ctrl_knob_1 ==0){
    var_a == 0;}
 }

 constraint c_var_b {
  if(ctrl_knob_2 ==1) {
    var_b == 1; }
 }
 
 constraint c_ctrl_knob {
  if(ctrl_knob_1 ==1) {
    ctrl_knob_2 !=1; }
 }

endclass

class child_cfg_data extends base_cfg_data
 
 constraint c_var_a {
  var_a == 100;
 }

 constraint c_var_b {
  var_b == 200;
 }

endclass

In the above code the base constraints c_var_a and c_var_b is overrided which I dont want.
My constraints should be controlled by the knobs I use.
During randomization the ctrl_knob_1 ==0, but I notice that the var_a==100.

Any help is well appreciated.

Regards
DRX

2

In reply to DoDo_Drx:

You can declare variables
local and provide accessor methods to get their values. But users will not be able to constrain them in derived classes.

3

In reply to dave_59:

Hi Dave ,

Can Constraint Blocks be also declared as local ? . I went through the LRM for the syntax of a constraint but it only explained about static constraints .

My Confusion arises since constraints are members like functions/tasks and properties

Regards,

AGIS

4

In reply to Etrx91:

That is currently not allowed. There is an open enhancement request for this.