How to resolve random stability or how to get diff random values at each instance

SystemVerilog
1

Hi,

I am a RTL designer and need to change the SV code for some bug.

Initially we are using $urandom variable in one of the SV model.
This causing issue : at any simulation tick-time, all parallel instance of the above said SV model is having same Random value. Which is not true in real time.

So we tried with $random, which giving different values at each SV model instance. but we see “random stability” issues like if someone changes the TB code, they are not able to re-produce the old results.

Can you please help me how to overcome this.

I am not familiar with SV but studies couple of docs on random stability, Still not clear how to proceed.

2

In reply to ramananda:

$urandom is the recommended method to solve stability issue. do not use $random

but all parallel instance having same random value could be solved by seeding that differently.
process proc; //create a process variable
int unsigned seed;

proc = process::self();
proc.srandom(seed); // do this before you call urandom in instances…

you can pass different seeds to different instances from some top module (hierarchically). you generate those seeds using urandom at top module. this gives you both stability (per simulation seed) and randomness to different instances…
assuming your parallel instances are modules, but similar thing applies for objects…instead of process you must use object.srandom

let me know if that works…

3

In reply to ssureshg_:

Thanks,

I have implemented similar kind. by making SEED value as a Parameter, so that the DV user can give unique seed for all instances.

Regards.

4

In reply to ramananda:
but parameter would make all sim runs behave the same, try port instead or even hierarchical access…
one more thing is this fixes only one thread, make seed of all other threads a derivative of this…like +1 or mod or something like that…