How to pass parameterized objects to a function as argument

SystemVerilog
1

I have a parameterized class(A). I want to pass its handle to a function in another class. But the simulator gives error,when I pass a handle to an object which is parameterized to a non-default values.
Example:

class A #(int a=1);
...
endclass

class B_seq extends uvm;
A #(1)a1;
A #(2)a2;
A #(3)a3;

function func1(A a)
.....
endfunction

task body;
func1(a1);
func1(a2);
func1(a3);
endtask
endclass

In the above case when for func1(a1),it doesnt give any error because its parameter value is same as default value.But for
func1(a2)
func1(a3)

it gives error saying,
formal and actual donot have assignment compatible datatypes. Expecting class::A#(1) but found class::A#(2)
How can I pass a2 and a3 to the same function??

Thanks

2

You can do

class A#(int a) extends A_base;
endclass
class B_seq extends uvm;

function void funct1(A_base a);

But then you need to provide more detail about what this code is trying to do.

3

In reply to dave_59:

I have 32 ports and each port has defined space in memory into which I need to write certain descriptors.
Class A has the variables and descriptors per port and I’m parametrizing the class with the start addr of each port.My idea is,by taking objects of this class ,I can mimck the same behavior for all the ports.

In the function func1, I want to take the value of one descriptor and generate another descriptor for the same port and write it into the corresponding ports’ space in memory

class B_seq extends uvm_sequence;
 A a1;
A a2
A a3;

task body()
.....
if(port==1)
func1(i,a1);
else if(port ==2)
func1(i,a2);
else
func1(i,a3);
endtask;


function func1(int i,A this_a);
bit[31:0] cnt;

cnt=this_a.hdr[127:96];
......
backdoor_write_to_mem(this_a.cnt_addr,cnt);
endfunction
endclass

Dave,
with your idea,I should cast the received object into corresponding ports’ object.Please correct me if I’m wrong.

4

In reply to kartavya:

The above code worked even without casting.Thanks

5

In reply to dave_59:

Hi dave ,

I tried this-
class A#(int a) extends A_base;
endclass
class B_seq extends uvm;
function void funct1(A_base a);

A_base in my case is uvm_port_base.
class A is uvm_analysis_port#(parametrized transaction class)
function void funct1(A a);–> Is giving compatibility error as described by first problem.
function void funct1(A_base a)–> It is throwing error as hierarchical name component failed at ‘get_port_type’ while elaborating. file pointed- uvm_port_base.svh
Do you have any suggestions for resolution for this?

Regards,
Ragini