How to pass a class array variable to module?

SystemVerilog
1

Hi.

I’m trying to pass a a class array variable to module.
I can successfully make randomized array in a class. But how to pass the array into the module?
I faced error message when I use class array in the module directly.
How do I correctly pass the array from class to module?


                                                                         
interface rnd_interface;
logic clk=0;
logic reset;
logic [3:0] rnd_out;
logic [3:0] q[];
endinterface

class rnd_num_c;
  virtual interface rnd_interface rnd_intf;
  rand logic [3:0] q[];
  rand int wsize;

  constraint size_con{
    wsize inside {[0:10]};
    q.size() == wsize;
}
endclass

module test;
logic rstn=0;

rnd_interface intf();

initial begin
  rnd_num_c rnd_num;
  rnd_num = new();

  if(!rnd_num.randomize())
    $error("randomization fail");

  foreach(rnd_num.q[i]) begin
    intf.q[i] = rnd_num.q[i];
    $display("rnd_num.q[%0d]=%0d",i, rnd_num.q[i]);
  end
end

always #5 intf.clk = ~intf.clk;

logic  [3:0] seq;
logic [3:0] i=0;

always@(posedge intf.clk or negedge rstn) begin
  if(!rstn) begin
    seq <= 0;
    i <= 0;
  end else begin
    i <= i+1;
    seq <= intf.q[i];
    $display("seq[%0d]=%0d", i, intf.q[i]);
  end

...
2

In reply to UVM_LOVE:

The scope of ‘rnd_num’ is local to the initial block, so you can’t access it anywhere else. You want to make it a variable of the module ‘test’:


`timescale 1ns/1ns

interface rnd_interface(input bit clk, input bit reset);
  logic [3:0] rnd_out;                                                        
  logic [3:0] q[]; // I just make q[] array to get from rnd_num_c class's q.
endinterface

class rnd_num_c;                                                            
  virtual interface rnd_interface rnd_intf;                                 
  rand logic [3:0] q[];                                                     
  rand int wsize;
    
  constraint size_con{                                                      
    wsize inside {[0:10]};                                                  
    q.size() == wsize;                                                      
  }                                                                           
endclass
    
module test;                                                                
  logic clk=0;                                                                
  logic rstn=0;
  
  rnd_interface intf(.clk(clk), .reset(~rstn));
  rnd_num_c rnd_num = new();                                                        
  
  initial begin                                                               
    if(!rnd_num.randomize())                                                  
      $error("randomization fail");
    
    foreach(rnd_num.q[i]) begin                                               
      $display("rnd_num.q[%0d]=%0d",i, rnd_num.q[i]);                         
    end                                                                       
  end
  
  initial begin
    clk = 0;
    forever #5 clk = ~clk;
  end

  initial begin
    rstn = 0;
    repeat (10) @(posedge clk);
    rstn = 1;
  end
  
  initial begin  // Logic to end the simulation since there is no other endpoint
    #500;
    $finish();
  end
  
  logic [3:0] seq;
  logic [3:0] i=0;
  
  always@(posedge clk or negedge rstn) begin
    if(!rstn) begin
      seq <= 0;
    end
    else begin
      seq <= rnd_num.q[i++];
    end
  end
endmodule

Be careful because your always block can use an index greater than the size of rnd_num.q