How To Initiliaze Nonresettable JK Latch Gate Level Model in Verilog/Systemverilog

SystemVerilog
,
1

Hi All,
I want to initialize a gate-level JK Latch output (q & q_bar with some value),please find below the code for same:

//JK Latch Gate Level verilog code
module jk_ff(output q,q_bar,input j,k,en);
wire j,k;
wire q,q_bar;
wire en;
wire q_w;
wire q_bar_w;
wire j_w,k_w;

//AND Gate primitive instance
and k_and (k_w,en,q_w,k);
//NOR Gate Primitive Instance
nor k_nor (q_w,k_w,q_bar_w);
//AND Gate primitive instance
and j_and (j_w,en,q_bar_w,j);
//NOR Gate Primitive Instance
nor j_nor (q_bar_w,j_w,q_w);

assign q = q_w;
assign q_bar = q_bar_w;
endmodule

//Test Bench JK Flipflop
module tb_jk_ff();
reg tb_j,tb_k,tb_en;
wire tb_q,tb_q_bar;
//instantiate design module
jk_ff uut (.j(tb_j),.k(tb_k),.en(tb_en),.q(tb_q),.q_bar(tb_q_bar));
initial begin
   tb_j = 1'b0;
   tb_k = 1'b1;
   #1 tb_en = 1'b0;
   #4;
   tb_en = 1'b1;
   #1 tb_en = 1'b0;
repeat(2)
 begin
#5 tb_en=1'b1;
#5; 
tb_j = 1'b1;
tb_k = 1'b1;
#1 tb_en =1'b0;
tb_j = 1'b0;
tb_k = 1'b0;
$monitor("@time:%0t==tb_en=%b,tb_j=%b,tb_k=%b,tb_q=%b,tb_q_bar=%b",$time,tb_en,tb_j,tb_k,tb_q,tb_q_bar);
$dumpfile("jkff.vcd");
$dumpvars(0,tb_jk_ff);
end
end
endmodule

I am getting unknown value (x) on both q,q_bar output of RTL for all input combination.I have also tried by initialize RTL wire q_w & q_bar or by declaring reg for q,q_bar & then initialize but no avail. Can any one suggest a way to initialize gate primitive in such scenario.(Note: this code is bug free and can be simulated straight away)

Thanks.

2

In reply to VLSI ENTHU:
Have you considered using from the testbench the force/release for one time step? That should force the latch into a known state.

The procedural continuous assignments (using keywords assign and force) are procedural statements that allow expressions to be driven continuously onto variables or nets. The syntax for these statements is given in Syntax 10-4.
procedural_continuous_assignment ::= // from A.6.2
assign variable_assignment
| deassign variable_lvalue
| force variable_assignment
| force net_assignment
| release variable_lvalue
| release net_lvalue
variable_assignment ::= variable_lvalue = expression
net_assignment ::= net_lvalue = expression // from A.6.1
Syntax 10-4—Syntax for procedural continuous assignments (excerpt from Annex A)

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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