How to force all bits of the signal at same time?

SystemVerilog
1

Is there any way to force all bits of signal at same time?
Because i see like p0_addr[4] first than p1_addr[3] and so on…

1]
initial begin
fork
force dut.p0_addr[4] = spi_dma_if.dma_addr[4] ;
force dut.p0_addr[3] = spi_dma_if.dma_addr[3] ;
force dut.p0_addr[2] = spi_dma_if.dma_addr[2] ;
force dut.p0_addr[1] = spi_dma_if.dma_addr[1] ;
join
end

define force(out,in,sel,st0=strong0,st1=strong1)\ always @(in,sel iff(sel === 1'b1))\ begin\ wait(sel === 1'b1);\ force out = in;\ end\ force ( dut.p0_addr[1] ,spi_dma_if.dma_addr[1] , 1’b1,supply0,supply1 )
force ( dut.p0_addr[2] ,spi_dma_if.dma_addr[2] , 1'b1,supply0,supply1 ) force ( dut.p0_addr[3] ,spi_dma_if.dma_addr[3] , 1’b1,supply0,supply1 )
`force ( dut.p0_addr[4] ,spi_dma_if.dma_addr[4] , 1’b1,supply0,supply1 )

2

In reply to saurabh_4710:

It would certainly help to see all the declarations of signals involved. Assuming the bits in your signals are all ordered high to low, you can do

initial force dut.p0_addr[4:1] = spi_dma_if.dma_addr[4:0] ;

There’s no need for a fork/join in the code you have shown. Each force is a background process anyways.

Your second code example makes no sense to me at all. You define macro arguments st0 and st1 with default values, then call the macro using the same default values, and then never use the arguments in the macro. Also, there’s no need to use a always block because a force is a continuous assignment that executes in the background whenever the RHS changes. You could have written the macros as`

define force(out,in,sel)\
initial wait(sel === 1'b1) force out = in;

`force ( dut.p0_addr[4:1] ,spi_dma_if.dma_addr[4:1] , 1'b1)