How do I iterate through hdl hierarchy with foreach/generate loop

SystemVerilog
,
1

Hi,

I want to reduce the number of lines in my code by iterating though hdl hierarchy with foreach loop so that instead of 10 individual force statement I can write a reduced code.

Example,

module test();

  test_interface my_interface[10];

  assign my_interface[0].addr = dut.mod0.addr;
  assign my_interface[2].addr = dut.mod2.addr;
  ..
  ..
  assign my_interface[9].addr = dut.mod9.addr;

endmodule

For above code I want to do something like this,

module test();

  test_interface my_interface[10];
  
  foreach(my_interface[i]) begin
    assign my_interface[i].addr = dut.mod/i/.addr;
  end

endmodule

Is it even possible to iterate hdl hierarchy like this? If yes then how it can be achieved?

2

In reply to MilanKubavat:

It is not possible to do this within SystemVerilog unless instead of manually instantiating mod0, mod1, …, mod9 individually, you had used an array of instances or a generate loop. Once you embed a number in an identifier, it become a single symbolic reference, no longer a string.

3

In reply to dave_59:

Thanks Dave for the response. I’ll go with manual instantiation of hdl hierarchies like,

assign my_interface[0].addr = dut.mod0.addr;
assign my_interface[1].addr = dut.mod1.addr;
…
…
assign my_interface[9].addr = dut.mod9.addr;