How to define array with multiple types

SystemVerilog
1

I have an array named “rand_arr” I have an array named rand_arr which supposed to contain various values from differnt types. I call the following random functiom for randomize the values in the array:

   function int my_randomize(int seed);
      int temp, success
      for (i = 0; i < rand_arr.size(); i++)
    begin
       temp = (($urandom(seed)) + 1);
       rand_arr[i] = temp - 1;
       suceess = (temp && suceess);
    end
      if(suceess == 0)
    return 0;
      else
    return 1;
   endfunction: my_randomize

Is there a way to define such an array in system verilog?

2

In reply to saritr:

By definition, an array is a collection of variables with identical types. I assume when you say “type” you just mean variables with different number of bits. You could create an array whose elements contain the maximum size of bits, and mask the extra bits.

Also, I have no idea what you are trying to do with temp and success.

3

In reply to dave_59:

Regarding the “type” issue:
Actually I have to fet different type (int, bit vector, enum. unpacked vector bit). I have to be able to rand those types… so maybe I have to use a class or a structure and go throgh all the its member.

Regarding the temp and success:
I was sure that in case of urandom() failure the return value is 0… but I thing I was wrong…

4

In reply to saritr:

There is no in-built mechanism to “go through all the members”…