How to check value of valid=1 in past for random cycle delay

SystemVerilog
1

Hi,

I am new to systemverilog assertion. I am trying to check if RLast always occurs (combining with RVALID and RREADY to make sure it’s valid case) before RID value changes. I can able to achieve if it’s in previous clock cycle using $past. But In this case the (RLast & RValid &RReady) = true in any random number of cycles before RID change. Below I have written it in statement I wanted to achieve.

Please help me on this.

property p;
(if RID value change) |-> (sample new RID value) and (check in past if RLast &RValid&RReady=true & RID= new RID value)
endproperty

always @(posedge clk) assert property p();

2

The easiest way is to use the generate if “n” in the $past(n) is relatively small (e.g., <32). A modified example from my SVA Handbook 4th Edition
;


bit[2:0] v=3;
 ap_delay_fix: assert property( $rose(a) |-> $past(v) == b); // illegal 
// Can do this though 
generate for (genvar g_i=0; g_i<8; g_i++) begin
  ap_delay_gen: assert property (v==g_i && $rose(a) |-> $past(v) == b);
end endgenerate

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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