How to check randc variable is generating different values?

SystemVerilog
,
1

Say you have a 5 bit randc variable. How will you check that for the first ten times the value is different?
We need to write a checker and not a generator (hence constraint will not work).

I would appreciate help on this. Thanks!

2

In reply to rosebud:



            // After call to Obj.randomize()
   if (  ( Obj.random_c_variable inside { local_q }  ) ) // Your checker
      `uvm_error( ... )
   else
       local_q.puh_back( Obj.random_c_variable ) ;