How can we generate randc behaviour from rand variable

SystemVerilog
1

If I want to generate randc functionality from rand variable , How can we achieve that .

2

It’s easy to get the first cycle of random numbers by pushing values on a list in post_randomize() and adding a constraint that keeps the values in the list excluded from the next solution.

class A;
   rand mytype_t myvar;
   mytype_t list[$];
   constraint cycle { unique {myvar,list};}
   function void post_randomize;
      list.push_back(myvar);
   endfunction 
endclass

The real problem is knowing when to start the cycle over by clearing the list. If the exact number of possible values for myvar is known, you can add a pre_randomize() method that deletes the list when hitting that limit.

function void pre_randomize;
 if (list.size() == limit) list = {};
endfunction

Otherwise you will have to check the result of calling randomize() and assume it fails because it has exhausted the list of values.

3

In reply to dave_59:

Thanks Dave , Got it :)

Also I have one more question which is Can we connect Driver and Sequencer with analysisn ports and Scoreboard and monitor with seq_item_port/export? If not why ?