Getting Error-[ISRF] Illegal scoped reference found

SystemVerilog
, ,
1

Hi All,
I am unable to get this code compiled.
Kindly help me out with this error

Error:
**Error-[ISRF] Illegal scoped reference found
design.sv, 6
“\this .get_width.a”
Scoped reference to the non-static class task/function
‘pass_width::get_width’ is not allowed.

1 error
CPU time: .783 seconds to compile**
Thanks in advance

SV Code:


class pass_width;
  logic [3:0] z;
  
task get_width(logic a);
  static logic c = a;
  force z=c;
endtask

task get_size();
  static logic a = 1;
  get_width(a);
endtask

      
endclass
2

In reply to Dilsya:

Static variables, regardless of their declaration location, get initialized once before time 0. That is before the get_width() method gets called. I believe you want

task get_width(logic a);
  static logic c;
  c = a;
  force z=c;
endtask