Hi ,
I am trying to assign some 768 bits pins values using generate block and getting compilation error , can anyone help with this regards ?
// Code your testbench here
// or browse Examples
module temp();
logic [767 : 0] xi_h ;
logic [7:0][7:0][63:0] pins_out;
// assignment of PO outputs to the XOMUX_H inputs
generate
//genvar gp512;
//genvar gp64;
for (genvar i=0; i<64; i++) begin
for(genvar j=0;j<2;j++)begin
genvar gp512 = i[5:3];
genvar gp64 = i[2:0];
assign xi_h [ 0 + 12 * i + j * 6] = pins_out [gp512] [gp64] [6 + j*32];
assign xi_h [ 1 + 12 * i + j * 6] = pins_out [gp512] [gp64] [7 + j*32];
assign xi_h [ 2 + 12 * i + j * 6] = pins_out [gp512] [gp64] [8 + j*32];
assign xi_h [ 3 + 12 * i + j * 6] = pins_out [gp512] [gp64] [9 + j*32];
assign xi_h [ 4 + 12 * i + j * 6] = pins_out [gp512] [gp64] [10 + j*32];
assign xi_h [ 5 + 12 * i + j * 6] = pins_out [gp512] [gp64] [11 + j*32];
end
end
endgenerate
endmodule
Error-[SE] Syntax error
Following verilog source has syntax error :
“testbench.sv”, 16: token is ‘=’
genvar gp512 = i[5:3];
^
1 error
CPU time: 1.826 seconds to compile
Exit code expected: 0, received: 1