Getting an compilation error on concurrent assertion

SystemVerilog
1

Hi,

I have written an assertion mentioned below:

  1. property clk_stop;
  2. @ (negedge CLK_STP_CLK_PATH.clkext2f) disable iff (!tb_A9Platform.assertions_on) !CLK_STP_PATH.nCPURESET ##1 CLK_STP_PATH.nCPURESET |-> (CLK_STP_PATH.CLK == 1’b0)[*3] ##1 (`CLK_STP_PATH.CLK == 1’b1);
  3. endproperty

clk_stop_assertion : assert property (clk_stop)
else $display(“clk_stop_assertion failed for hold the clk zero for total of three cycles”);

I am getting the following compilation error.

Expecting the keyword endmodule at line 2, though i have written endmodule for my module.
Please help.

Regards,
Shailendra