Function in class without new reserved word

SystemVerilog
1

What is the difference between these 2 functions (first one with new and second one without) or when should i use each one of them ?

class test;

bit [7:0] a;

bit [7:0] b;

bit [7:0] c;

function new (input bit [7:0] a='b0, b ='b0, c ='b0);

  this.a = a;  //To deal with data members having same name as function argument

  this.b = b;

  this.c = c; 

endfunction



function void display(input int counter);

  $display("Counter=%0d, Value of a=%0d, b=%0d, c=%0d",counter,a,b,c);

endfunction



endclass
2

In reply to Farah_Adel_Fathy:

This is one of the most basic principle of classes in SystemVerilog. Please see my course SystemVerilog OOP for UVM Verification, or any other introduction to object oriented programming.