Forever inside a task

SystemVerilog
1

Hello,

Can you put a forever inside a task in SystemVerilog ?

module FJ;
  logic clk1=0;
  
  task T;
    forever
      begin
        #10 clk1 = ~clk1;
      end
  endtask
  
  initial
    begin
      T;
      #100;
      $finish;
    end
  
  initial
    begin
      $dumpvars;
      $dumpfile("tb.vcd");
    end
  
endmodule

Thanks,
JeffD

2

Yes, it is legal to use a forever inside a task, and it is a very common practice.

However, in your code, when you call the task, it will never end, and you will never reach the #100; statement.

In this case, it is common to call the task inside a fork/join_none construct:


  initial
    begin
      fork
          T;
      join_none
      #100;
      $finish;
    end

This starts the task, but it does not wait for it to finish.