In reply to Thanu:
In both of these assertions "out" has in its binary decision tree the inputs "sel a b".
Thus, I would say that the tools drive those inputs in the identical manner, and those
two assertions are equivalent.
In this topic of formal verification I strongly recommend the book
Formal Verification: An Essential Toolkit for Modern VLSI Design by Erik Seligman, Tom Schubert, M V Achutha Kiran Kumar, ISBN: 9780128007273. That book covers essential aspects of formal verification, including theory; practical tips derived from actual usage of formal verification and from real designs; various approaches, or angles of attack, in using formal verification when verifying different types of designs and situations; and test case examples, and progression of solutions in achieving the end goals.
Ben Cohen
http://www.systemverilog.us/
For training, consulting, services: contact http://cvcblr.com/home
* SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
* A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
* Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
* FREE this week at AMZN: Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
* Component Design by Example ", 2001 ISBN 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
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1) SVA Alternative for Complex Assertions
https://verificationacademy.com/news/verification-horizons-march-2018-issue
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3) SVA in a UVM Class-based Environment
https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment
4) https://verificationacademy.com/forums/announcements/free-book-component-design-example-%E2%80%A6-step-step-process-using-vhdl-uart-vehicle
