Flag to check the ref_clk is toggling or not

SystemVerilog
1

Hi,

I have written the code which assert the flag when clock is off and de-assert the flag when clock is available.

But below code is not generating as per the expected. it is generating one pulse of ref_clock_toggling, when clock is off and again once pulse when i turn on the clock .

Expectation : ref_clock_toggling should be 1 when ref_clk is present and should be 0 when is turn off the clock.

Note : i_mon_clk can or can not be equal to ref_clk (its independent from each other )

Edit code - EDA Playground

module top; 
    `include "uvm_macros.svh"
    import uvm_pkg::*;
    logic i_mon_clk=1'b1, a, b; 
    logic i_ref_clk=1'b1; 
    initial forever #5 i_mon_clk = !i_mon_clk; 
    initial forever #10 i_ref_clk = !i_ref_clk; 
bit ref_clk_toggling;
initial begin 
  #100;
  repeat(2) @(posedge i_mon_clk); 
  forever begin : fvr
    @(posedge i_mon_clk);
    if ((i_ref_clk) == $past(i_ref_clk,1 ,,@(posedge i_mon_clk)) ) ref_clk_toggling<=1'b0;    
else ref_clk_toggling<=1'b1;
   end : fvr
 
   end 
  
  initial 
    begin
      #1000;
      force top.i_ref_clk = 0;
      #1000;
      release top.i_ref_clk;
      #1000;
      $finish;
    end 

  endmodule

Could anyone help me?

2

you can use $stable to simplify the code.


module top;
    //`include "uvm_macros.svh"
    //import uvm_pkg::*;
    logic i_mon_clk=1'b1, a, b, c;
    logic i_ref_clk=1'b1;
    initial forever #5 i_mon_clk = !i_mon_clk;
    initial forever #10 i_ref_clk = !i_ref_clk;

bit ref_clk_toggling;

initial begin
  #100;
  repeat(2) @(posedge i_mon_clk);
  forever begin : fvr
    @(posedge i_mon_clk);
    ref_clk_toggling=!$stable(i_ref_clk,@(posedge i_mon_clk));
  end : fvr
end

  initial
    begin
      $monitor("%t ref_clk_toggling=%0d", $time, ref_clk_toggling);
      #1000;
      $display("%t stopping ref clock", $time);
      force top.i_ref_clk = 0;
      #1000;
      $display("%t starting ref clock", $time);
      release top.i_ref_clk;
      #1000;
      $finish;
    end

  endmodule

output::
0 ref_clk_toggling=0
120 ref_clk_toggling=1
1000 stopping ref clock
1010 ref_clk_toggling=0
2000 starting ref clock
2010 ref_clk_toggling=1

3

In reply to Alokpati:

Hi Alok,

Thank you for reply. it works well when

    initial forever #5 i_mon_clk = !i_mon_clk;
    initial forever #10 i_ref_clk = !i_ref_clk;

But it does not work with

    initial forever #10 i_mon_clk = !i_mon_clk;
    initial forever #5 i_ref_clk = !i_ref_clk;

In my case ref_clk and mon_clk can have any frequency .