FIFO_DEPTH

SystemVerilog
1

Could you please help me out in the following query :

Why it is always that FIFO depth is set to 16-bytes in RTL design ?

Thanks
Susmita

2

In reply to sush:
Where did you read that?

3

It was asked in one interview question . Do you agree ?

4

In reply to sush:
You probably need to work on your search skills first, then read Calculating FIFO Depth