Hello all,
I don't know if that's the right for inquiries, but I would like to see support for (true) anonymous aggregate data types (à-la C++), and packed union with different size members. For example, an AMBA CHI's RSP flit would look like:
struct packed {
...
union packed {
logic data_pull;
chi_state_t fwd_state;
}; // Anonymous union, namely speaking.
...
} chi_rsp_flit_t;This would permit to have more readable, complex structures. Fields can share the same set of bits on buses to save space, but this isn't done in the first place. That is, designer sometimes do a first iteration without common fields, then do a second round packing as much as what can be. With current SystemVerilog's specification, such structure would look like this:
struct packed {
...
union packed {
struct packed {
logic[$bits(chi_state_t)- 1:1] res0;
logic data_pull;
} alt1;
struct packed {
chi_state_t fwd_state;
} alt0;
} cf0;
...
} chi_rsp_flit_t;which is difficult to read and not scalable, especially when implementing common fields as a second step, as described before. Indeed, when moving from flat to common fields, not only shall the structure definition be modified, but also all the RTL and verification code that instance this structure. With anonymous aggregate data types, this code won't have to be touched. And with packed union supporting members with different size, there is no need to create an extra layer in the hierarchy.
I know there is a revision of the SystemVerilog standard being written. Do you think that would be possible to incorporate such features? If that's not the right place to ask, please redirect me to the correct one.
P.-S. This question may have been already asked. I apologize if that's the case.
