Extending TB Timeout

SystemVerilog
,
1

Currently when running my bit_bash test I observe TB timeout message as ::

UVM_FATAL @ 40000000.00000ns: reporter [PH_TIMEOUT] Explicit timeout of 40000000.00000ns hit, indicating a probable testbench issue

In my base_test I have following code ::


 time  hd_time ;

 //  Within  build_phase  
     hd_time = ( (cfg_h.timeout_in_ms * (10**9))*1ns );
     uvm_top.set_timeout(hd_time);
    `uvm_info("BASE_TEST",$sformatf("hd_time=%0t",hd_time),UVM_NONE)

The output I observe for these info message is ::


UVM_INFO @ 0.00000ns: uvm_test_top [BASE_TEST] hd_time=18446744073414584320.00000ns

Would it be possible from build_phase() of my ral_test which extends base_test to override the timeout ?

For eg I would prefer the simulation to run 10 times the previous value

2

In reply to MICRO_91:

Communicating time values across multiple timescale domains has been a gotcha in Verilog since day one. Timescales only apply to scaling of literal time values, not values of variables or passed arguments. You need to know the timescale in effect when the UVM package was compiled and make sure the value passed to set_timeout is in those units. If it was in picoseconds, then you need to call the timeout using

hd_time = ( cfg_h.timeout_in_ms * 1ms / 1ps );

Your ral_test::build_phase() can call uvm_top.set_timeout() after it calls super.build_phase(). Last setting wins.