Event trigger multiple times in same time stamp

SystemVerilog
,
1

I want to know the scheme in systemverilog to catch the event in same timeslot.

Code is like,

uvm_event e;

process 1:
repeat(2) begin
  e.trigger();
end

process 2:
forever begin
  e.wait_trigger();
  //...
end

process 1 and process 2 are running in parallel. It seems like it failed to catch the earlier trigger in the same time slot. Note in my case wait_trigger is called before e.trigger. How systemverilog handle this case?

2

In reply to runxuanl:

I suggest you use a mailbox instead of an event. Or you need to put a delay in the repeat loop.