Error while fetching the associative array of queue

SystemVerilog
1 
class storage extends uvm_component();
`uvm_component_utils(storage)

/*new constructor*/

axi_transaction mem[int][$];

//axi_transaction ia a sequence_item handle that has awlen,ardata,wdata[$],rdata[$]... as properties

endclass



inside monitor component :: 
  axi_tx.rdata.push_back(vif_h.wdata); //axi_tx is the handle for seq_item
  axi_tx.wstrb = vif_h.wstrb;
  axi_tx.wlast = vif_h.wlast;
  axi_tx.wready= vif_h.wready;
  axi_tx.wvalid= vif_h.wvalid;
  $cast(axi_a,axi_tx.clone());

  storage_h.mem[1].push_back(axi_a);
$display("\t a_array_value = %p",storage_h.mem[1]);

output :
// mem:‘{1:’{@axi_transaction@15} },

i am unable to display the elements inside the memory,its displaying class name

inside driver ::
axi_tx_1h = storage_h.mem[1].pop_front(); // the pop_front is not collecting the data from the memory.
so while driving the data to the vif_h, im getting fatal error.
vif_h.rdata<=axi_tx_1h.rdata.pop_front();

waiting for the positive response.

2

In reply to Abhisek Sarkar:

The storage_h handle in monitor component is the same as the one in driver component?
Can you show your code that you share the storage handle between driver and monitor.

3

In reply to cuonghle:

Yes, i am seting the storage using config db and getting.

4

In reply to Abhisek Sarkar:

The LRM does not explain how %p with class objects. It only says to display as if assigned using an assignment pattern, and assignment patterns are not defined for use with classes.

You might try:

foreach ( storage_h.mem[1][i]) $display("\t a_array_value = %p",storage_h.mem[1][i]);