Edge sensitive and level sensitive - assertion rules

SystemVerilog
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1

Hi,

I have the following 3 questions w.r.t the assertion rules when it comes to edge-sensitive and level-sensitive implementation.
Kindly clarify.

  1. Can concurrent assertions be only edge-sensitive? If so, please explain why?

  2. Can immediate assertions be both edge and level sensitive? Please explain why and why not.

  3. Can deferred immediate assertions be both edge and level sensitive?

Thanks in advance.

2

In reply to sk7799:

Concurrent assertions are based on events for describing behavior over a sampled series of events. That event can only be defined as a change in a signal, and further qualified with a posedge or negedge.

Immediate assertions have no concept of sensitivity—they evaluate when the procedural code they appear in are executed. That procedural code could have edge, level, or combinatorial sensitivity; or could be in code with no sensitivities.