Does Randcase use Seed values?

SystemVerilog
, , ,
1

Exactly what the title says,

My function uses randcase to generate some weighted random distribution. I was wondering if


randcase
        5 * is_first : begin
          chosen_index = first_index;
          address      = first_address;
        end
        4 * is_second: begin
          chosen_index = second_index;
          address      = second_address;
        end
        1 * is_third : begin
          chosen_index = third_index;
          address      = third_address;
        end
endcase

uses seed values? How would I set it through command line? Is there another way that can accomplish this better?

Thanks in advance.

2

In reply to jimmyhuang0904:

This was clarified in the 1800-2017 LRM. randcase uses the same process seeding as $urandom. You can change the master seed with a tool specific command (look that up in the User Manual) or you can change the process seed by calling the srandom() method.