Does SystemVerilog support operator overloading?

SystemVerilog
1 
  function bit bitl(logic v);
    return (v == 1);
  endfunction

  function bit bitr(real v);
    return (v <= 2.0) && (v >= 1.58);
  endfunction

  bind = function bit bitl(logic);
  bind = function bit bitr(logic);

Does not compile, yield “syntax error” do I miss something ?

2

In reply to spauls:
Operator overloading was removed from the IEEE 1800-2017 LRM. From what I remember, the weak type system from Verilog that SystemVerilog inherits made it difficult to implement without a lot more specification.