I am studying DMA and I have questions regarding to DMA. Questions are listed below, everyone will be highly appreciated to answer them and help me to understand the working of DMA.
Q1) When DMA is a flow controller, in which condition hardware handshaking interface will be used or software handshaking interface will be used for either source or destination peripherals?
Q2) Is the hardware handshaking interface also includes single and burst request signals along with request and acknowledge signals?
Q3) When source or destination peripheral is flow controller then why hardware handshaking interface is not supported?
Q4) When DMA is a flow controller (means DMA knows the block size and DMA should transfer the data using maximum possible bursts and where possible using single or early-terminated burst), then why do peripherals request for single or burst transactions?
Q5) For peripheral-to-memory, memory-to-peripheral and peripheral-to-peripheral single or multi-block transfers, if the peripheral is either source or destination then address to read from source and address to write on destination should be fixed throughout the single or multi-block transfer. Is this a correct statement?
Q6) I have confusions in DLR (DMA Line Router) that how it selects a set of service sources from a set of DMA compatible service sources? Then how the selected service sources are further used for hardware handshaking? Kindly refer me to any resource from which I can understand the working of DLR. And also refer some resources for priority Mux for handling hardware requests from DLR.
Thanks for the reply, I have been studying DMA provided by the Infineon in xmc-4100_xmc-4200 micro-controller series.
For my first question, I know why hardware and software handshaking is used but in what conditions, we need to use hardware or software handshaking when DMA is flow controller.
For my second question, I have studied that for hardware handshaking, peripheral requests DMA for transfer, then DMA acknowledges it that indicates transfer is completed and if the request from peripheral is still high then DMA will do the transfer again. I have also studied that there are single or burst request signals in peripherals (depending it is receiver, transmitter or transceiver) so does hardware handshaking interface also accommodate the single and burst request signals along with request and acknowledge signals?
For my third question, I have studied that hardware handshaking is not supported when peripheral is a flow controller if this is depend on the specification of the IP then kindly give me the reason why hardware will not be supported?
For my forth question, I have studied that when DMA is flow controller then it knows the DMA transfer size (block size). Then it will transfer the data using maximum possible burst length if the block size is multiple of burst length (unless software will not limit the burst length) and using single or early-terminated burst if block size is not multiple of burst length, so why there is a need for peripheral to request for single or burst transactions?
For my fifth question, according to my understanding, mostly peripherals have only one memory mapped register for Tx or Rx separately so for peripheral-to-memory, memory-to-peripheral and peripheral-to-peripheral single or multi-block transfers, if the peripheral is either source or destination then address to read from source and address to write on destination should be fixed throughout the single or multi-block transfer. Is this a correct statement if not then why?
For my sixth question, I have studied that in Infineon document that for hardware handshaking interface DLR (DMA Line Router) is responsible and I have almost understood how it is doing it but I want more clarity with its working. So can you please provide any document for it and also for priority muxing to handle these hardware requests in DMA.