Distribution in constraints

SystemVerilog
1

I want to write some data (few registers address ) into file for which I have written constraints distribution.

Ex: I suppose I have two registers A, B and their address is 100 and 101 respectively and I want address 100 to be written 10 times and 101 to be written 2 times in the file (100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 101, 101). if the number of times the register needs to be written in file is not same as given in parameters driver will stuck.

So the issue is after randomizing the number of times the register written in file is not exactly same as given through parameters. Sometimes it works fine but some times it stucks.

Please suggest some solution for same.

2

In reply to ksharma30:

randc int count;
rand  bit[31:0]  addr;
 
constraint count_range { count inside {[0:9]}; }
constraint my_dist { 
   if (count < 2) 
        addr==101;
   else
        addr==100;
}

See distributed weightage constraint | Verification Academy

3

In reply to dave_59:

Thanks Dave, I try this solution if it work fine otherwise I will share my logic for file generation .