difference between static casting and dynamic casting in system verilog?
In reply to lalithjithan:
Dynamic casting with $cast is for down-casting class object from a base class variable to an extended class variable. Since you do not know until run-time what type of object a base variable holds, the check cannot be performed until runtime. One normally tests the successfulness of a $cast, so that is considered “dynamic”. Please see my SystemVerilog OOP course on classes for more details on up-casting versus down-casting and how that relates to inheritance. Dynamic casting has no affect on the value of the object being casted
Static casting in SystemVerilog is unrelated to OOP. Since SystemVerilog has no pointers, the only use of static casting is to change the format or interpretation of a value from one type to another (unsigned to signed). Static casting has the potential to change the value being cast (logic to bit). Static casting is mainly used to change the shape of an array or struct from one type to another while still preserving each bit. See bit-stream casting in the LRM.