Difference between relational operators in constriants

SystemVerilog
1

Intent: Get ascending order of values for a, b and c;
What is the difference between the two constraints ?
First Constraint gives an incorrect answer. Why?
Second constraint works correctly . Why ?

      rand int a, b , c;
     `ifdef CHECK
        constraint c_abc        {  0 < a < b < c; }
     `else 
        constraint c_abc        {  0 < a;
                                   a < b;
                                   b < c; }
      `endif
2

This_link would help .

3

In reply to ABD_91:
Editted the question.

4

In reply to diptishe:

The link provided by ABD_91 describes what is happening, read the penultimate paragraph.
“…After looking at the output from EDAPlayground: ‘{A:3, B:1, C:4}, I can see that those values satisfy the constraint because the expression gets evaluated as (A <= B) <= C;
Substituting those values we have (3’d3 <= 3’d1) is 1’b0, and (1’b0 <= 3’d4) is 1’b1, so the solver is able to pick those values as a solution…”

HTH,

-R