difference between linear test bench and self checking test bench and in systm verilog and UVM the test bench is linear or selfchecking?
In reply to lalithjithan:
Normally a linear testbench is one where the stimulus and/or expected results are hardcoded in a linear fashion with no variation based on the DUT’s behavior. Think of a DUT memory where you make a request to write data to an address, and then make a request to read it back. Strictly speaking, a linear testbench would have the stimulus timed exactly to meet the bus protocol without even looking for grants or acknowledgment from the DUT.
The term self-checking usually refers to predicting the results. You can have linear stimulus with self-checking results. In the previous DUT memory example, the testbench could observe(monitor) that write request and then when the request occurs, match the data written with the data read.
You can certainly have non-linear or random stimulus without self-checking the results (no-ckecking). In that case you will either visually inspect the results (yes, people still do this), or verify the results with some other tool after the simulation completes.
The UVM has many facilities to help you incorporate random stimulus and self-checking test benches, but there are no requirements forcing you into doing it that way.