Diff between @(posedge clk); and @(posedge clk) begin/end

SystemVerilog
1 
forever begin

@(posedge clk);
vif.w_en<=txn.w_en;
vif.w_data<=txn.w_data;
....
...

end

forever begin

@(posedge clk)
begin
vif.w_en<=txn.w_en;
vif.w_data<=txn.w_data;
....
...
end
end

In 2nd forever block w_en and w_data are sampled at posedge of clk, can anyone explain even for 1st forever block also w_en and w_data are sampled at posedge of clk?? or i it will add one clock cycle delay??

2

In reply to kathula venkatesh:

There is absolutely no difference in the execution of the two loops. You could even write it as

forever  @(posedge clk) begin
   vif.w_en<=txn.w_en;
   vif.w_data<=txn.w_data;
   ....
   ...
 end

Delay and @signal or timing controls that prefix any single procedural statement. (See verilog - Difference between @(posedge Clk); a<= 1'b1; and @(posedge Clk) a<= 1'b1; - Stack Overflow)
begin/end is single procedural statement use to group a serial set of statements.

3

In reply to dave_59:

Thankyou sir for your reply, but i have another doubt which is

for example

forever begin
@(posedge clk);
vif.w_en<=txn.w_en;
vif.w_data<=txn.w_data;
…
…
vif.w_data_out<=txn.w_data_out;
end

here vif.w_data_out<=txn.w_data_out; //which is not supposed to be sample at posedge clk for that is it mandate to use begin/end to @(posedge clk)? or any other way?

4

In reply to kathula venkatesh:

forever begin
@(posedge clk);
vif.w_en<=txn.w_en;
vif.w_data<=txn.w_data;
…
…
vif.w_data_out<=txn.w_data_out;// write this statement outside the begin so that it will not take place at posedge clk.
end

5

In reply to agoel:

In reply to kathula venkatesh:
forever begin
@(posedge clk);
vif.w_en<=txn.w_en;
vif.w_data<=txn.w_data;
…
…
vif.w_data_out<=txn.w_data_out;// write this statement outside the begin so that it will not take place at posedge clk.
end

hi agoel,

there i didn’t mention begin/end to @(posedge clk); that’s y i am asking whether it is required begin/end or not?