Defining adoptable width of variable size

SystemVerilog
1

Hi,

I want to give size of address space as “rand reg a[:50]”, where the empty part is the maximum size. I think I have seen it somewhere that we can define it in this way. But my compilation is failing with syntax error. I tried giving a[:50], where will assume the maximum value but then it is failing that address must be bounded. How can I define it that upper limit it can assume the maximum value?

Regards,
Pankaj

2

In reply to papatel:

You might be confusing a bounded queue, which is an unpacked array, with something else

rand logic a[$:50]; // a bounded queue of 1-bit variables with max 50 elements.

Width is a packed array dimension, but it must have a fixed width at compilation.

rand logic [0:49] a; // a 50-bit integer variable

It would help to explain values you expect as valid solutions.