Default auto_bin_max value for cross coverage

SystemVerilog
1

Could you please clarify what is the auto_bin_max default value for cross of a,b in the following code.it seems the value is not 64


module sri;
bit  [3:0] a;
bit  [3:0] b;

covergroup cg;
   cross a,b;
endgroup

initial begin
   cg c=new();
end

endmodule
2

In reply to srbeeram:
According to table 19-2 in the 1800-2017 LRM, auto_bin_max does not apply to cross bins. You should see 256 bins. There may be some tool specific limits preventing run-away specifications.