Declare a logic vector with a variable size

SystemVerilog
1

I am not sure if this is possible, but what I am trying to do in the code below is to create a logic vector called “message” inside of a task, but the size of this vector depends on one of the inputs to the task:


task send_lwir_cmd(
    input [7:0] sequence_count,
    input [7:0] message_id,
    input [7:0] packet_size,
    input [127:0] payload,
    input [15:0] checksum
    );

    logic [(packet_size+5)*8:0] message = 0;
    logic [31:0] header_id = 31'h1A9933A1; // always the same header ID
    
    begin
        ...

I want to be able to call this task multiple times using a different value for ‘packet_size’. Is this possible to do? I know it would work if I made packet_size a localparam but I want to be able to change it when I call the task.

2

In reply to ianmurph:

You probably want an unpacked dynamic array instead of a packed array.

    logic [7:0] message = new [packet_size+5];