Cross Coverage

SystemVerilog
, , ,
1

Hi
I am actually learning coverage and I was trying example of cross coverage but I am unable to sample the values fully every time I run the code its giving 75 and not 100 what’s the issue in this??

module cross_cover;
bit [1:0]a[8]='{0,1,2,3,0,1,2,3};
bit [1:0]b[8]='{0,1,2,3,0,1,2,3};
bit[1:0]x,y;


covergroup cg@(posedge clk);
coverpoint_y:coverpoint y;
coverpoint_x:coverpoint x;
cross_xy:cross coverpoint_y,coverpoint_x;
endgroup

cg cg1=new;
initial
begin
      for(int i=0;i<8;i++)
	 begin
	  x=a[i];
          y=b[i];
	end
     $display(cg1.get_inst_coverage);
end
endmodule
2

In reply to nishita_tailor:

You didn’t show how clk was generated to sample the covergroup, but assuming it did 8 samples, I don’t see how you would have gotten more than 50%. coverpoint_x/y have 4 bins each that are all hit (8 bins). But cross_xy has 16 bins of which you only hit 4. So there are only 12 bins hit out of a total of 24 bins which is 50% coverage.

To get 100% coverage you need all 16 bins of cross_xy hit. You would need

bit [1:0]a[16]='{0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3};
bit [1:0]b[16]='{0,1,2,3,1,2,3,0,2,3,0,1,3,0,1,2};