Covergroup instance issue - system verilog

SystemVerilog
,
1

Hi,

I am trying to take instance of covergroup in a uvm_class but tool giving error while taking instance.

class ref_model extends uvm_component;
bit [3:0] states;
`uvm_component_declare(ref_model)
covergroup cg_fsm_state ;
c1 : coverpoint states;
endgroup
cg_fsm_state cg_fsm_state_inst;
function new (string name,uvm_component parent);
super.new(name, parent);
endfunction
endclass

Error I am getting as below,

Error-[SE] Syntax error
Following verilog source has syntax error :
token ‘cg_fsm_state’ should be a valid type. Please declare it
virtual if it is an Interface.
“/vobs/cores/infrastructure/cia_resourcecontrol/aon_mod_verif/sim/models/./aon_mod_fsm_ref_model.sv”,
208: token is ‘;’
cg_fsm_state cg_fsm_state_inst;

I am not getting why tool not allowing to take instance of covergroup?

Regards,
Smit

2

In reply to Smit Govani:

Please read the LRM section 19.4 Using covergroup in classes, in this case the covergroups cannot be instantiated and an anonymous covergroup is created.
HTH,

-R