Coverage using functions like $onehot and $countones on the bit[31:0]

SystemVerilog
1

Hi,

I am trying to add coverage for when half the bits are set in the variable “bit[31:0] foo” and one only one bit is set. I tried this:


covergroup fcov with function sample(bit [31:0] foo); 
    cp1 : coverpoint foo {
        function count_ones(bit [31:0] foo) begin
           count_ones.push_back($countones(foo) == 16);
        endfunction
        function one_hot(bit [31:0] foo) begin
           one_hot.push_back($onehot(foo));
        endfunction

        bins half_set  = count_ones(foo);
        bins one_set = one_hot(foo);
        bins other = default; 
    } 
  endgroup

VCS is not accepting it.
Error-[SE] Syntax error
Following verilog source has syntax error :
token is ‘function’
function count_ones(bit [31:0] foo) begin

I wrote that based on a snippet from the 2012 SV userguide(19.6.4.1).

module mod_m;
logic [31:0] a, b;
covergroup cg(int cg_lim);
coverpoint a;
coverpoint b;
aXb : cross a, b
{
function CrossQueueType myFunc1(int f_lim);
for (int i = 0; i < f_lim; ++i)
myFunc1.push_back('{i,i});
endfunction
bins one = myFunc1(cg_lim);
bins two = myFunc2(cg_lim);
function CrossQueueType myFunc2(logic [31:0] f_lim);
for (logic [31:0] i = 0; i < f_lim; ++i)
myFunc2.push_back('{2*i,2*i});
endfunction
}
endgroup
cg cg_inst = new(3);
endmodule

I guess I can accomplish this using some more variables but I was wondering why this isn’t working.

2

In reply to Pooja Pathak:

A couple of problems with your code. You are only allowed to declare functions within cross definitions. That’s so you can take advantage of the built-in typedef CrossQueueType that is unique to each cross. The other problem is you cannot use a sampling argument(foo) in a bin expression; bins get created when the covergroup is constructed. They do not change for each sample.