Continuous assignment

SystemVerilog
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1

Hello,

A bit rusty on Verilog. It’s been a while.

Came across the following in a RAM model.

assign data = (!nCS && !nOE) ? mem[address] : 32’bZ;

As I know, Continuous assign gets evaluated every time any of the variables on the RHS change. Question is will this particular expression get evaluated every time nCS, nOE or address change? Or will it get evaluated only when nCS and nOE change?

Thanks.

2

In reply to a72:

You answered your own question. Continuous assign gets evaluated every time any of the variables on the RHS change.

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In reply to dave_59:

Thanks Dave. Knew the answer, but wanted to double confirm.