I am able to compile below code with out errors but during simulation I could see following ERROR
Error: Variable ‘readdata’ written by continuous and procedural assignments. See test.sv(7).
Could Simulate same code with Synopsys VCS successfully without any issues.
Is there any switch available in Questa to get compile and simulate without doing any modifications in RTL.
module test #(parameter DATA_WIDTH = 1);
logic [63:0] readdata;
assign readdata[(DATA_WIDTH*32)-1:0] = 32'h1234_5678;
always_comb
for (int i = DATA_WIDTH*32; i < 63; i = i+1)
readdata[i] = ~readdata[i-1];
initial
begin
$monitor("readdata is %h",readdata);
end
endmodule
Your code violates the SystemVerilog LRM. Section 6.5 states:
An assignment where the left-hand side contains a slice is treated as a single assignment to the entire slice.
Thus, a structure or array can have one element assigned procedurally and another element assigned
continuously. And elements of a structure or array can be assigned with multiple continuous assignments,
provided that each element is covered by no more than a single continuous assignment.
The precise rule is that it shall be an error to have multiple continuous assignments or a mixture of
procedural and continuous assignments writing to any term in the expansion of a written longest static prefix
of a variable (see 11.5.3 for the definition of a longest static prefix).
Why would you want a tool to allow you to violate the LRM? You should instead fix your code to follow the LRM requirements.
I want to add that this forum is not for tool specific support. But there may be a way to suppress the error - contact your vendor directly for support or read the user manual. I want to stress that suppressing this error might be OK to do on a known working design. But you will get erratic behavior when unintentionally mixing procedural and continuous assignments to the same variable. There is no way to determine when the continuous assignment should override the procedural.
True as wrote above by Dave if you are able to suppress this error anyhow by any means but the above RTL piece of code is not going to give a reasonable functionality
There is no conflict in the above RTL code. The
for loop iterates over bits that do not overlap the same bits as the continuous assignment. It just happens that one particular compiler recognizes one particular use case and does not generate an error. Add any more complexity to it and it will generate an error even though there is still no overlap
module test #(parameter DATA_WIDTH = 1);
logic [63:0] readdata;
assign readdata[(DATA_WIDTH*32)-1:0] = 32'h1234_5678;
always_comb
for (int i = DATA_WIDTH*32; i < 63; i = i+1)
readdata[f(i)] = ~readdata[i-1];
function int f(int arg);
return arg;
endfunction
initial
begin
$monitor("readdata is %h",readdata);
end
endmodule