Constraint to generate a clock

SystemVerilog
,
1

I am trying to develop a constraint to produce a clock (successive 0 and 1s) with out the use of other variables

This is the code I used

constraint value {
                a dist {1:=1 , 0:=1};
		a inside {0,1}; 
                 }

But I am not getting the expected answer.
What change I should make to get the desired output?

2

In reply to bachan21:

can you show how you declared the variable “a”
if we declare the variable as randc a; it will work
// in this case , we can’t use dist constraint

3

In reply to bachan21:

Can you please explain what you are expecting and what you actually get?

4

In reply to naveetha:

Hi Naveetha,
I am declaring variable ‘a’ as a byte.
With bit your method with randc will work
I have been asked this question in an interview.
There my interviewer had mentioned to declare it as byte

You thoughts?

5

In reply to dave_59:

Hi Dave,
My intention is to write a constraint that will generate clock behavior when randomized multiple times.

Expected output : 0,1,0,1,0,1,0,1,0…

Observed Output : 0,1,0,1,1,1,0,0,1…

6

In reply to bachan21:

byte also works with randc right?
module tb;

class fun;
randc byte clk;
constraint clock {
//clk dist {1:=1 , 0:=1};
clk inside {0,1};

}
endclass
fun obj;
initial begin
obj = new();
for(int i =0; i<6;i++)begin
obj.randomize();
$display(“clk val is %b”,obj.clk);
end
end
endmodule

output:
clk val is 00000001
clk val is 00000000
clk val is 00000001
clk val is 00000000
clk val is 00000001
clk val is 00000000

7

In reply to naveetha:

Hi Naveetha
This is the output I get

#1 clk val is 00000000
#2 clk val is 00000001
#3 clk val is 00000000
#4 clk val is 00000001
#5 clk val is 00000001
#6 clk val is 00000000

You can see, on line 5, the expected behavior is not met.

Cyclic randomization does not guarantee any particular behavior.
After 0,1 is completed, next repetition may either 0,1 or 1,0.

So If we are getting 0,1,1,0 the behavior is not met

8

In reply to naveetha:

I have just copied your code and ran it on QuestaSim
No changes had been applied

P.S. just using randc and inside constraint wont guarantee 0,1,0,1,0,1 behavior as cyclic behavior is not exactly predictable. So we need to constraint it further or update the existing.

9

In reply to bachan21:

The only one way to write this constraint with only one variable is using a const cast.

module top;
  class clk;
    rand byte a;
    constraint value {
      if (const'(a)) a==0; else a==1;
    }               
  endclass
  clk h = new;
  initial repeat (20) #1 begin void'(h.randomize); $write("%0d",h.a); end
endmodule

You might want to see this post about distributions, and this post about const casts.