Constraint 0 < variable < 50

SystemVerilog
,
1

Hi,

Is this valid constraint in system verilog ?

constraint con_c{ 0 < c < 50;}

It gives below output.

pkt2.c= 45
pkt2.c=102
pkt2.c= 1
pkt2.c= 34
pkt2.c= 36
pkt2.c= 54
pkt2.c= 72
pkt2.c=124
pkt2.c= 66
pkt2.c= 45

2

In reply to DhavalP:

try below constraint
constraint con_c{ c inside{[0:50]};}

3

In reply to DhavalP:

Please read the following Asking better questions on the Verification Academy Forums with EDAPlayground - Verification Horizons to understand the problem with your constraint.