Constrained input generation in increasing order

SystemVerilog
,
1

I wish to generate an input in such a way that all possible cases are covered in the form of a ramp. So if it is a 4 bit data, the input to the DUT should be 0000, 0010, 0100, … 1111. Any idea how this can be done?

2

In reply to geek_vlsi:

I get that that the next number is 1000, but what comes after that?

3

It basically needs to cover all cases. In this case 2^4 cases in increasing order (ramp) in order to test the DUT for all possible inputs.

Like:
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
.
.
.
1111

4

In reply to geek_vlsi:

That’s a different series than in your first post. That’s just a for-loop with a delay (you didn’t specify how often the input should change.

5

Thank you for your reply. The difficulty is that my testbench is performing another operation ; something of error injection. This module repeats for a few cyles. I want the generator to be a separate module and for every input that is generated for the DUT, I want my error module to alter the data and send it to the DUT.

So basically, input needs to ramp up by 1 ; error module should use this data and iterate over a few cycles by adding errors in different positions; then the input needs to ramp up by 1 again and go back to error module and repeat the same process. I do not know how to implement this.