Compare unpacked array

SystemVerilog
1

Why these code have error?

module tb;
  //  TransactionIn tr;
    bit s[5];
    initial begin
        s = {0,1,0,1,1};
        if(s ==[0,1,0,1,1])
            $display("yes");
    //tr = new();
    end
    
endmodule

module tb;
  //  TransactionIn tr;
    bit s[5];
    initial begin
        s = {0,1,0,1,1};
        if(s =={0,1,0,1,1})
            $display("yes");
    //tr = new();
    end
    
endmodule
2

In reply to Moein75:

You need to read section 10.9 Assignment Patterns of the LRM.

You are using concatenation instead of positional assignment. You want:


module tb;
  bit s[5];
  initial begin
    s = '{0,1,0,1,1};
    if (s =='{0,1,0,1,1})
      $display("yes");
  end
endmodule