Clocking-Block Clocking Event Scheduling

SystemVerilog
1

I want to understand when the clocking events of the clocking blocks are scheduled (exactly in which event region).
Are they scheduled/triggered in the active event region or observed event region.
In LRM we have below code

clocking cb @(negedge clk);
  input v;
endclocking
always @(cb) $display(cb.v);
always @(negedge clk) $display(cb.v);

And LRM says second always-block is prone to race condition unlike the first one.
Please help me understand this.

2

In reply to Aryan:

The clocking block event @(cb) is scheduled as soon as the event control @(negedge clk) occurs. This is usually in the active region where clk gets updated. Note that the postponed, preponed, and observed regions cannot schedule new events or update values, they are read-only.

When declaring a signal as a clocking block input, there are three values you need to think of

  1. The raw signal value at the current time in the current region
  2. The sampled signal value — in the default input skew case, the signal’s value at the end (postponed) of the previous time step.
  3. The clocking block input signal value — This value gets updated with the sampled value just prior to triggering the clocking block event.

Think of a clocking block written as another always block

bit v;
bit cb_v;
event cb;
always @(negedge clk) begin
     cb_v = $sampled(v);
    ->cb;
  end
always @(cb) $display(cb_v);
always @(negedge clk) $display(cb_v);

There is a race condition between the first and third always blocks because you don’t know if you are getting the new or old value of cb_v.

The second always block has no race because the update to cb_v uses a blocking assignment and the trigger happens afterwards. Using a non-blocking assignment would have removed the race, but then the clocking block input value would not be available for another clock cycle.

My general rule when using clocking blocks is only use the clocking block event and do not mix any other event controls within that process.

3

In reply to dave_59:

Thank you for the detailed explanation. The new example clarified my doubt.