Hello,
We can generate clock in this many ways.
bit clk = 0;
clk = !clk;
or clk = ~clk;
or clk +=1;
what difference make this three statements. is there any changes at hardware level?
Thanks in Advance.
Hello,
We can generate clock in this many ways.
bit clk = 0;
clk = !clk;
or clk = ~clk;
or clk +=1;
what difference make this three statements. is there any changes at hardware level?
Thanks in Advance.
In reply to Dhanesh_Padia:
I use
The ! is the logical not or inversion operator of its value and produces a value of 1 0r 0, true or false (no vector)
- The ~ is bitwise invert operator. Thus on a vector of v=101, the ~v has the value 010.
Obviously, for a 1 bit vector, the ~ and the ! produce the same results.
However, they have different connotations. I prefer the ! (meaning invert, true/false result, of the value of the vector)
- The clk +=1; works, but does not make sense, and adder?
- *is there any changes at hardware level?*
Actually, the clock is never synthesized and is generated externally via a crystal clock oscillator with very tight tolerances on the frequency.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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* [SVA Handbook 4th Edition, 2016 ISBN 978-1518681448](http://goo.gl/JOfuEB)
* [Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712 ](https://goo.gl/d10QHh)
* A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
* Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
* Component Design by Example ", 2001 ISBN 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
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See Paper: 1) https://verificationacademy.com/forums/systemverilog/vf-horizonspaper-sva-alternative-complex-assertions
2) http://systemverilog.us/vf/SolvingComplexUsersAssertions.pdf