Choosing between covergroup and cover property

SystemVerilog
,
1

Hi ,

I tried an alternate solution using cover property for a recent thread .


 property  trans ;
    
     @( posedge clk )  ( data == 2 )  |=>  ( data == 3 )  ##1  ( data != 2 )[*0:$]  ##1  (  data == 2 )  ##1 ( data == 3 ) ; 

   endproperty

 cover  property ( trans )  $display(" TIME:%2t  Transition  Occurred " , $time );

*Note that [0:$] isn’t valid for bins

I was curious how does a DV person choose implementation between : functional coverage ( using bins ) V/S cover property ?

Here are a few points I noted down :
(1) Reason to implement using Functional Coverage :

  • Valid within class ( cover property can’t be written within class ).
  • Selective bins possible using with_clause / set_covergroup_expression

(2) Reason to implement using cover property :

  • Rich set of constructs to cover complex sequence / scenario .
  • Allows $ as upper bound ( not valid for bins )

Both can be written within module , interface , program , package .

Any further reasons that could be added to choose one over the other ?

EDIT : Complex Pattern :: 2 3 4 6 2 7 2 3 Should NOT be Covered !!

    Limitation  of  using  code  from  previous [thread](https://verificationacademy.com/forums/coverage/transition)  is  that  the  pattern  is  covered  whereas  using  cover  property  it  isn't  covered
2

In reply to Have_A_Doubt:

You have captured the main points. I would simplify this to say that cover directives are best for temporal/protocol scenarios and fit well inside an interface.

3

In reply to dave_59:

Thanks Dave .

Also I would like to add that temporal cases with multiple clocks could be easier to cover via cover property .