Case statment

SystemVerilog
,
1

Hi

I used with case below:

always @(posedge force_sig_en)begin //{
      if(io_sig_direction_arr[force_sig_id] == DIRECTION_IN)begin //{
         case(force_sig_id)
           'h001:begin
              force adc       = 1'b1;    
              force dbg_io    = 1;
            end
            'h004:begin
               force DFI      = 1'b1;
               force dbg_io_  = 4;
            end
            'h006:begin
               force adc       = 1'b1;
               force dbg_io    = 2;
            end
            'h007:begin
               force ts_2      = 1'b1;
               force dbg_io    = 3;
            end
           'h00a:begin
               force ch_in    = 1'b1;
               force gpio_io  = 5;
            end
            'h00b:begin
                force adc      = 1'b1;
                force gpio_io  = 0;
            end
           'h00e:begin
                force DFI      = 1'b1;
                force gpio_io  = 1;
             end
       endcase
      end //}
   end //}

when force_sig_id ==1,
I would have expected that only forces related to Case 1 would be made.
And in practice there are forces related to other cases.

What is the error in the code?

2

In reply to saraTel:

You need to release the other forces.

3

In reply to dave_59:

I don’t understand why FORCE is made for cases that differ from 1,
while the value for comparison is 1

4

In reply to saraTel:

I don’t understand it either with the code you show.