Can we use a distribution on enum variable?

SystemVerilog
1

Hi,

This is regarding enum distribution. Refer the example code below.

typedef enum int {error_type_1 = 1, error_type_2 = 2, error_type_3 = 3} error_type;
rand error_type select_error_type;

In this case it will randomly pick the error_type.

but, I would like to add the distribution.
say, 30 percent for error_type_1, 30 percent for error_type_2 and 40 percent for error_type_3.

Is it possible with enum declarations?

2

*In reply to prashanth.billava:*Yes, a dist constraint works with an enum.

3

In reply to dave_59:

Hi Dave,

Thanks for quick reply. Just one more clarification.
Is this the right syntax for that? I couldn’t get any examples in LRM.

typedef enum int {error_type_1 = 1 := 30, error_type_2 = 2 := 30, error_type_3 = 3 := 40} error_type;
rand error_type select_error_type;

Thanks in advance,

4

In reply to prashanth.billava:
enum constraint example code based on your code



typedef enum int {error_type_1 = 1 , error_type_2 , error_type_3 } error_type;
rand error_type select_error_type;

constraint c_error_type {
   select_error_type dist {error_type_1:/30,error_type_2:/30,error_type_3:/40};
}
5

In reply to kddholak:
This solution for some reason does not work for me.